Verilog Design, Synthesis, and Netlisting of IoT-Based Arithmetic Logic and Compression Unit for 32 nm HVT Cells

Micro-processor designs have become a revolutionary technology almost in every industry. They brought the reality of automation and also electronic gadgets. While trying to improvise these hardware modules handle heavy computational loads, they substantially reached limit size, power efficiency, similar avenues. Due constraints, many manufacturers corporate entities are ways optimize mini beasts. One such approach is design microprocessors based on specified operating system. This came limelight when companies launched their microprocessors. In this paper, we will look into one method using an arithmetic logic unit (ALU) module for internet things (IoT)-enabled devices. A specific set operations added classical ALU help fast processes IoT-specific programs. We integrated compression multiplier Vedic algorithm 16-bit module. The designed synthesized under 32-nm HVT cell library from Synopsys database generate overview areal levels, layout module; it gives us netlist database. synthesis provides complete how be manufactured if sent foundry.